{"id":2707,"date":"2023-08-06T17:34:48","date_gmt":"2023-08-06T17:34:48","guid":{"rendered":"https:\/\/www.emprog.com\/emprog\/product-devalert-copy\/"},"modified":"2024-02-18T20:29:55","modified_gmt":"2024-02-18T20:29:55","slug":"machineware","status":"publish","type":"page","link":"https:\/\/www.emprog.com\/emprog\/machineware\/","title":{"rendered":"Product MachineWare"},"content":{"rendered":"<div class=\"wpb-content-wrapper\">[vc_row][vc_column width=&#8221;1\/6&#8243;][\/vc_column][vc_column width=&#8221;2\/3&#8243;]<div class=\"heading-box col-lg-9 col-md-8 col-sm-8\"><h1 class=\"box-title\">MachineWare SIM-V Virtual Prototyping for RISC-V<\/h1><\/div>[vc_empty_space height=&#8221;20&#8243;][\/vc_column][vc_column width=&#8221;1\/6&#8243;][\/vc_column][\/vc_row][vc_row][vc_column width=&#8221;1\/4&#8243;][\/vc_column][vc_column width=&#8221;1\/2&#8243;][vc_column_text]\n<p style=\"text-align: left;\"><span style=\"font-family: arial, helvetica, sans-serif; color: #1b4268; font-size: 18pt;\">Virtual Prototyping<\/span><\/p>\n[\/vc_column_text][vc_empty_space height=&#8221;20&#8243;][vc_column_text]\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">We offer a leading Virtual Prototyping and Simulation platform supporting a Full System Simulation. SIM-V platform is indispensable for any embedded software development using RISC-V minimizing the complexity and challenges of building a complex SoC before any H\/W availability. With a fast, flexible, non-intrusive, and easy to use Virtual Simulation platform you can accelerate your overall design. SIM-V Virtual Prototype (VP) simulates your hardware at bit-level accuracy, shortening development time and enhancing software security, stability, and quality. Our VP supports single or multi-core designs that include any number of RISC-V cores, Arm cores or others. You design it, we simulate it! <\/span><\/p>\n[\/vc_column_text][\/vc_column][vc_column width=&#8221;1\/4&#8243;][\/vc_column][\/vc_row][vc_row][vc_column width=&#8221;1\/4&#8243;][\/vc_column][vc_column width=&#8221;1\/2&#8243;][vc_empty_space height=&#8221;32&#8243;][vc_column_text]\n<p style=\"text-align: left;\"><span style=\"font-family: arial, helvetica, sans-serif; color: #1b4268; font-size: 18pt;\">RISC-V<\/span><\/p>\n[\/vc_column_text][vc_empty_space height=&#8221;20&#8243;][vc_column_text]\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">RISC-V is a customizable, open-standard Instruction Set Architecture without license cost or legacy baggage, but with the flexibility to realize your ideas. Today\u2019s most-used software stacks, such as Linux, Android and Chrome, already run on RISC-V and more are to follow &#8211; from Embedded to HPC. Get on board today. SIM-V is built on decades of experience in ultra-fast, interoperable simulation technology. Leverage our solutions to jumpstart your RISC-V project and begin development now.<\/span><\/p>\n[\/vc_column_text][\/vc_column][vc_column width=&#8221;1\/4&#8243;][\/vc_column][\/vc_row][vc_row][vc_column width=&#8221;1\/4&#8243;][\/vc_column][vc_column width=&#8221;1\/2&#8243;][vc_empty_space height=&#8221;32&#8243;][vc_column_text]\n<p style=\"text-align: left;\"><span style=\"font-family: arial, helvetica, sans-serif; color: #1b4268; font-size: 18pt;\">SIM-V<\/span><\/p>\n[\/vc_column_text][vc_empty_space height=&#8221;20&#8243;][vc_column_text]\n<p><span style=\"font-family: arial, helvetica, sans-serif; color: #808080; font-size: 12pt;\">SIM-V is ultra-fast, functional RISC-V instruction set simulator (ISS). It enables you to verify your RISC-V software before hardware becomes available. Its rapid simulation speed reduces test runtimes, enabling your teams to reap detailed results sooner. All the while reducing energy consumption and saving time and money.<\/span><\/p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; color: #808080; font-size: 12pt;\">SIM-V is a cutting-edge RISC-V simulator, designed for high-speed and reliable performance. It empowers users to conduct thorough verification of RISC-V target software, including RTOS, Linux, and Android, well in advance of the availability of physical prototypes.<\/span><\/p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; color: #808080; font-size: 12pt;\">Use SIM-V simulator to validate any of your RISC-V designs even before physical prototypes are available. With its rich debugging, introspection and analysis features you can find bugs and security vulnerabilities before they can become a threat. Scale your simulations on-premise or in the cloud to reap results sooner. Enhance cross team communication with a shared tool. Give yourself an edge over competitors by adopting SIM-V early in your design cycle.<\/span><\/p>\n<p><strong><span style=\"font-family: arial, helvetica, sans-serif; color: #808080; font-size: 12pt;\">SIM-V Highlights:<\/span><\/strong><\/p>\n[\/vc_column_text][vc_column_text css=&#8221;.vc_custom_1691345800154{margin-left: 30px !important;}&#8221;]\n<ul style=\"list-style-type: disc;\">\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">Fast, functional simulators<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">Parallel RISC-V Full-System Simulation<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">SW development and verification<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">Architecture exploration<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">Shift-left: Better software earlier<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">Easy to use and integrate<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">Intuitive API and user interface<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">Well documented<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">Bring your own environment<\/span><\/li>\n<\/ul>\n[\/vc_column_text][\/vc_column][vc_column width=&#8221;1\/4&#8243;][\/vc_column][\/vc_row][vc_row][vc_column width=&#8221;1\/4&#8243;][\/vc_column][vc_column width=&#8221;1\/2&#8243;][vc_empty_space height=&#8221;32&#8243;][vc_column_text]\n<p style=\"text-align: left;\"><span style=\"font-family: arial, helvetica, sans-serif; color: #1b4268; font-size: 18pt;\">SIM-V Extension SDK<\/span><\/p>\n[\/vc_column_text][vc_empty_space height=&#8221;20&#8243;][vc_column_text]\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">Customizability is at the heart of RISC-V. With our intuitive SIM-V extension SDK you can quickly add custom instructions and registers to SIM-V. Simply plug your extension into our RISC-V reference model and get immediate feedback on your design choices.<\/span><\/p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">With the SIM-V Extension SDK, users can effortlessly incorporate their own customizations into SIM-V, ranging from instructions and registers to CSRs and beyond. Additionally, SIM-V verified RISC-V reference models serve as an excellent foundation for expediting your development. Get immediate feedback on your design choices with SIM-V, and unlock the full potential of your RISC-V projects.<\/span><\/p>\n<p><span style=\"font-size: 12pt; color: #808080;\"><strong><span style=\"font-family: arial, helvetica, sans-serif;\">SIM-V Extension SDK Highlights:<\/span> <\/strong><\/span><\/p>\n[\/vc_column_text][vc_column_text css=&#8221;.vc_custom_1691345862528{margin-left: 30px !important;}&#8221;]\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">\u27a2 Custom instructions, registers, CSRs and more<\/span><\/p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">\u27a2 RTOS, Linux, Android starting points available<\/span><\/p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">\u27a2 Easy-to-use C++ SDK<\/span><\/p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">\u27a2 SIM-V Custom Extensions<\/span><\/p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">\u27a2 Customization is a RISC-V USP<\/span><\/p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">\u27a2 SDK for extensions development<\/span><\/p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">\u27a2 No modifications to SIM-V<\/span><\/p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">\u27a2 Extension automatically loaded<\/span><\/p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">\u27a2 Leverage FTL for performance<\/span><\/p>\n[\/vc_column_text][vc_single_image image=&#8221;2716&#8243; img_size=&#8221;large&#8221; alignment=&#8221;center&#8221; css=&#8221;.vc_custom_1691346109368{margin-top: 20px !important;margin-bottom: 20px !important;}&#8221;][\/vc_column][vc_column width=&#8221;1\/4&#8243;][\/vc_column][\/vc_row][vc_row][vc_column width=&#8221;1\/4&#8243;][\/vc_column][vc_column width=&#8221;1\/2&#8243;][vc_empty_space height=&#8221;32&#8243;][vc_column_text]\n<p style=\"text-align: left;\"><span style=\"font-family: arial, helvetica, sans-serif; color: #1b4268; font-size: 18pt;\">SIM-V Virtual Platform<\/span><\/p>\n[\/vc_column_text][vc_empty_space height=&#8221;20&#8243;][vc_column_text]\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">Customizability is at the heart of RISC-V. With our intuitive SIM-V extension SDK you can quickly add custom instructions and registers to SIM-V. Simply plug your extension into our RISC-V reference model and get immediate feedback on your design choices.<\/span><\/p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">Simulating just the CPU might not be sufficient to cover all your use cases. Simulate your entire SoC by integrating SIM-V into a full-system simulator or Virtual Platform (VP). We offer starting point VPs for high-performance and embedded target applications based on our open-source modeling library VCML. By using VCML you can integrate our models into any SystemC-compatible simulation environment.<\/span><\/p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">Our Virtual Platform allows you to integrate SIM-V &amp; your designs using:<\/span><\/p>\n[\/vc_column_text][vc_column_text css=&#8221;.vc_custom_1691346264189{margin-left: 30px !important;}&#8221;]\n<ul style=\"list-style-type: disc;\">\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">Accellera SystemC TLM-2.0<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">MachineWare VCML<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">Open CPU Interface (OCX)<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">QEMU<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">Custom API<\/span><\/li>\n<\/ul>\n[\/vc_column_text][vc_empty_space height=&#8221;20&#8243;][vc_column_text]\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\"><strong>Virtual Platform Highlights:<\/strong><\/span><\/p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">&#8211; SIM-V is modular \u2013 pick the components that are right for you<br \/>\n<\/span><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">&#8211; Custom RISC-V instruction set extension SDK available<br \/>\n<\/span><\/p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">SIM-V is built on top of our innovative core technologies:<br \/>\n<\/span><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">&#8211; VCML \u2013 powerful SystemC TLM-2.0 modeling library<br \/>\n<\/span><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">&#8211; FTL \u2013 retargetable JIT-engine for high-speed CPU models<\/span><\/p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">* SIM-V is product designed and owned by MarchineWare GmbH<\/span><\/p>\n[\/vc_column_text][\/vc_column][vc_column width=&#8221;1\/4&#8243;][\/vc_column][\/vc_row][vc_row][vc_column width=&#8221;1\/4&#8243;][\/vc_column][vc_column width=&#8221;1\/2&#8243;][vc_empty_space height=&#8221;32&#8243;][vc_column_text]\n<p style=\"text-align: left;\"><span style=\"font-family: arial, helvetica, sans-serif; color: #1b4268; font-size: 18pt;\">InSCight: Profiling Virtual Platforms<\/span><\/p>\n[\/vc_column_text][vc_empty_space height=&#8221;20&#8243;][vc_column_text]\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">InSCight is a cutting-edge profiler designed for SystemC-based virtual platforms (VPs). It consists of two parts: The MachineWare SystemC simulation kernel that logs simulation data into a database during simulation runtime, and a desktop application that can load this simulation database and visualize the simulation data. Some of its highlights:<\/span><\/p>\n[\/vc_column_text][vc_column_text css=&#8221;.vc_custom_1697240699943{margin-left: 30px !important;}&#8221;]\n<ul style=\"list-style-type: disc;\">\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">Dynamically analyze profile simulations of Virtual Platforms.<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">Makes it easy to find and fix logical errors and bottlenecks in the simulation.<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">Improves the quality of the simulation results and the simulation performance.<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">Offers a solution for high-speed simulation.<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">Swiftly pinpoint and resolve performance bottlenecks, unlocking substantial performance enhancements.<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">Efficiently identifies slow-simulating models.<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">Empowers customers to maximize the potential of their virtual platforms.<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">Ensures optimal simulation speed for software development, regression testing and interactive debugging.<\/span><\/li>\n<\/ul>\n[\/vc_column_text][vc_column_text]\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">inSCight is indispensable in the context of virtual platforms, which are often composed of diverse models from various vendors and different abstraction levels. For more on InSCight, contact Emprog (<a href=\"mailto:info@emprog.com\" target=\"_blank\" rel=\"noopener\">info@emprog.com<\/a>)<\/span><\/p>\n[\/vc_column_text][\/vc_column][vc_column width=&#8221;1\/4&#8243;][\/vc_column][\/vc_row][vc_row][vc_column width=&#8221;1\/4&#8243;][\/vc_column][vc_column width=&#8221;1\/2&#8243;][vc_empty_space height=&#8221;32&#8243;][vc_column_text]\n<p style=\"text-align: left;\"><span style=\"font-family: arial, helvetica, sans-serif; color: #1b4268; font-size: 18pt;\">SystemC<\/span><\/p>\n[\/vc_column_text][vc_empty_space height=&#8221;20&#8243;][vc_column_text]\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">Since established as an IEEE standard, SystemC has emerged as the de-facto simulation environment for virtualization of complex systems. User\u2019s value its proven modeling flexibility and vendor interoperability. Those are the reasons that SystemC is widely adopted as the number one virtual system design environment today.<\/span><\/p>\n[\/vc_column_text][\/vc_column][vc_column width=&#8221;1\/4&#8243;][\/vc_column][\/vc_row][vc_row][vc_column width=&#8221;1\/4&#8243;][\/vc_column][vc_column width=&#8221;1\/2&#8243;][vc_empty_space height=&#8221;32&#8243;][vc_column_text]\n<p style=\"text-align: left;\"><span style=\"font-family: arial, helvetica, sans-serif; color: #1b4268; font-size: 18pt;\">QEMU Combined with SystemC<\/span><\/p>\n[\/vc_column_text][vc_empty_space height=&#8221;20&#8243;][vc_column_text]\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">Over the past decade, QEMU has become a fan-favorite of many companies due to its open-source nature and large developer community. It provides high-speed emulation of commonly used hardware, but lacks detail and interoperability. We offer a solution that enables integrating QEMU into standard SystemC.<\/span><\/p>\n<p><strong><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">MachineWare\u2019s QBox:<\/span><\/strong><\/p>\n[\/vc_column_text][vc_column_text css=&#8221;.vc_custom_1691346649746{margin-left: 30px !important;}&#8221;]\n<ul style=\"list-style-type: disc;\">\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">QEMU in a SystemC Box<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">SystemC + QEMU co-simulation<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">Flexible timing synchronization<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">All QEMU models available<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">Use cases<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">CPU subsystem integration<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">TLMification of legacy QEMU models<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">Open-source license<\/span><\/li>\n<\/ul>\n[\/vc_column_text][vc_single_image image=&#8221;2719&#8243; img_size=&#8221;large&#8221; alignment=&#8221;center&#8221; css=&#8221;.vc_custom_1691346709233{margin-top: 20px !important;margin-bottom: 20px !important;}&#8221;][\/vc_column][vc_column width=&#8221;1\/4&#8243;][\/vc_column][\/vc_row][vc_row][vc_column width=&#8221;1\/4&#8243;][\/vc_column][vc_column width=&#8221;1\/2&#8243;][vc_empty_space height=&#8221;32&#8243;][vc_column_text]\n<p style=\"text-align: left;\"><span style=\"font-family: arial, helvetica, sans-serif; color: #1b4268; font-size: 18pt;\">SERVICES<\/span><\/p>\n[\/vc_column_text][vc_empty_space height=&#8221;20&#8243;][vc_column_text]\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">We offer a list of services that can enhance the products we offer. A short example of service that can be offered:<\/span><\/p>\n[\/vc_column_text][vc_column_text css=&#8221;.vc_custom_1708287239894{margin-left: 30px !important;}&#8221;]\n<ul style=\"list-style-type: disc;\">\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">Virtual Platforms with VCML and SystemC<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">FTL Instruction Set Simulators<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">SIM-V (RISC-V ISS)<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">SIM-A (ARM ISS)<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">QBox<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">ARM-on-ARM<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">Services<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">SystemC, QEMU Modeling<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">Training &amp; Consulting<\/span><\/li>\n<\/ul>\n[\/vc_column_text][vc_single_image image=&#8221;2721&#8243; img_size=&#8221;large&#8221; alignment=&#8221;center&#8221; css=&#8221;.vc_custom_1691346855229{margin-top: 20px !important;margin-bottom: 20px !important;}&#8221;][\/vc_column][vc_column width=&#8221;1\/4&#8243;][\/vc_column][\/vc_row][vc_row][vc_column width=&#8221;1\/4&#8243;][\/vc_column][vc_column width=&#8221;1\/2&#8243;][vc_empty_space height=&#8221;32&#8243;][vc_column_text]\n<p style=\"text-align: left;\"><span style=\"font-family: arial, helvetica, sans-serif; color: #1b4268; font-size: 18pt;\">Arm Cortex-M<\/span><\/p>\n[\/vc_column_text][vc_empty_space height=&#8221;20&#8243;][vc_column_text]\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">We offer a leading Virtual Prototyping and Simulation platform supporting a Full System Simulation using Arm Cortex platform. SIM-A is indispensable for any embedded software development using Arm minimizing the complexity and challenges of building a complex SoC before any H\/W availability. <\/span><\/p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">SIM-A is a cutting-edge high-speed Arm architecture instruction set simulator. It is specifically designed to target Arm Cortex architectures. Leveraging the groundbreaking FTL (Fast Translator Library) technology of MachineWare, it empowers you to thoroughly validate your Arm software even before the hardware is accessible. Some of SIM-A highlights: <\/span><\/p>\n<p style=\"padding-left: 40px;\"><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">\u2022 Exceptional simulation speed, SIM-A significantly shortens test durations, allowing your teams to access comprehensive results more quickly.<br \/>\n<\/span><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">\u2022 Conserves energy and leads to substantial time and cost savings. <br \/>\n<\/span><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">\u2022 A novel instruction-set simulator for Arm Cortex architectures. <br \/>\n<\/span><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">\u2022 Derived from MachineWare\u00b4s proprietary Fast Translator Library (FTL).<br \/>\n<\/span><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">\u2022 Fast bring up complex software stacks, ranging from embedded Zephyr RTOS to Linux.<br \/>\n\u2022 Able to execute identical software as real hardware.<br \/>\n<\/span><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">\u2022 Help you in conquering the most challenging software development tasks with ease. <br \/>\n<\/span><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">\u2022 Best part is it complements our SIM-V product for high-speed RISC-V simulation.<\/span><\/p>\n<p><span style=\"font-family: arial, helvetica, sans-serif; color: #808080;\"><span style=\"font-size: 12pt;\">If you currently have or planning on using Arm core(s) in your SoC or IP, take advantage of our free consultation on best practices to simulate your entire SoC, email us at <a href=\"mailto:info@emprog.com\">info@emprog.com<\/a> to schedule a call and get more details.<\/span><\/span><\/p>\n[\/vc_column_text][\/vc_column][vc_column width=&#8221;1\/4&#8243;][\/vc_column][\/vc_row][vc_row][vc_column width=&#8221;1\/4&#8243;][\/vc_column][vc_column width=&#8221;1\/2&#8243;][vc_empty_space height=&#8221;32&#8243;][vc_column_text]\n<p style=\"text-align: left;\"><span style=\"font-family: arial, helvetica, sans-serif; color: #1b4268; font-size: 18pt;\">Demo<\/span><\/p>\n[\/vc_column_text][vc_empty_space height=&#8221;20&#8243;][vc_column_text]\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #808080;\">Online demos are readily available upon request. You can also take advantage of a free 30 mins telecon consultation on best practices to simulate your entire SoC or Embedded Application before any H\/W is available. Please email us at <a href=\"mailto:info@emprog.com\">info@emprog.com<\/a> for details.<\/span><\/p>\n[\/vc_column_text][vc_empty_space height=&#8221;32&#8243;][\/vc_column][vc_column width=&#8221;1\/4&#8243;][\/vc_column][\/vc_row][vc_row disable_element=&#8221;yes&#8221; el_id=&#8221;EvaluationForm&#8221;][vc_column width=&#8221;1\/4&#8243;][\/vc_column][vc_column width=&#8221;1\/2&#8243;][vc_empty_space height=&#8221;20&#8243;][vc_column_text]\n<p style=\"text-align: left;\"><span style=\"font-family: arial, helvetica, sans-serif; color: #1b4268; font-size: 18pt;\">SimV Evaluation &#8211; SandBox Request<\/span><\/p>\n[\/vc_column_text][vc_column_text]\n\n<div class=\"wpcf7 no-js\" id=\"wpcf7-f2701-o1\" lang=\"en-US\" dir=\"ltr\">\n<div class=\"screen-reader-response\"><p role=\"status\" aria-live=\"polite\" aria-atomic=\"true\"><\/p> <ul><\/ul><\/div>\n<form action=\"\/emprog\/wp-json\/wp\/v2\/pages\/2707#wpcf7-f2701-o1\" method=\"post\" class=\"wpcf7-form init\" aria-label=\"Contact form\" novalidate=\"novalidate\" data-status=\"init\">\n<div style=\"display: none;\">\n<input type=\"hidden\" name=\"_wpcf7\" value=\"2701\" \/>\n<input type=\"hidden\" name=\"_wpcf7_version\" value=\"5.9.5\" \/>\n<input type=\"hidden\" name=\"_wpcf7_locale\" value=\"en_US\" \/>\n<input type=\"hidden\" name=\"_wpcf7_unit_tag\" value=\"wpcf7-f2701-o1\" \/>\n<input type=\"hidden\" name=\"_wpcf7_container_post\" value=\"0\" \/>\n<input type=\"hidden\" name=\"_wpcf7_posted_data_hash\" value=\"\" \/>\n<input type=\"hidden\" name=\"_wpcf7_recaptcha_response\" value=\"\" \/>\n<\/div>\n<div class=\"row\">\n\t<div class=\"form-group col-sms-6 col-sm-6\">\n\t\t<p><span class=\"wpcf7-form-control-wrap\" data-name=\"first-name\"><input size=\"40\" class=\"wpcf7-form-control wpcf7-text wpcf7-validates-as-required full-width input-text\" aria-required=\"true\" aria-invalid=\"false\" placeholder=\"First name*\" value=\"\" type=\"text\" name=\"first-name\" \/><\/span>\n\t\t<\/p>\n\t<\/div>\n\t<div class=\"form-group col-sms-6 col-sm-6\">\n\t\t<p><span class=\"wpcf7-form-control-wrap\" data-name=\"last-name\"><input size=\"40\" class=\"wpcf7-form-control wpcf7-text wpcf7-validates-as-required full-width input-text\" aria-required=\"true\" aria-invalid=\"false\" placeholder=\"Last name*\" value=\"\" type=\"text\" name=\"last-name\" \/><\/span>\n\t\t<\/p>\n\t<\/div>\n\t<div class=\"form-group col-sms-6 col-sm-6\">\n\t\t<p><span class=\"wpcf7-form-control-wrap\" data-name=\"your-email\"><input size=\"40\" class=\"wpcf7-form-control wpcf7-email wpcf7-validates-as-required wpcf7-text wpcf7-validates-as-email full-width input-text\" aria-required=\"true\" aria-invalid=\"false\" placeholder=\"Email address*\" value=\"\" type=\"email\" name=\"your-email\" \/><\/span>\n\t\t<\/p>\n\t<\/div>\n\t<div class=\"form-group col-sms-6 col-sm-6\">\n\t\t<p><span class=\"wpcf7-form-control-wrap\" data-name=\"website\"><input size=\"40\" class=\"wpcf7-form-control wpcf7-text full-width input-text\" aria-invalid=\"false\" placeholder=\"Website\" value=\"\" type=\"text\" name=\"website\" \/><\/span>\n\t\t<\/p>\n\t<\/div>\n<\/div>\n<div class=\"form-group\">\n\t<p><span class=\"wpcf7-form-control-wrap\" data-name=\"company\"><input size=\"40\" class=\"wpcf7-form-control wpcf7-text wpcf7-validates-as-required full-width input-text\" aria-required=\"true\" aria-invalid=\"false\" placeholder=\"Company*\" value=\"\" type=\"text\" name=\"company\" \/><\/span>\n\t<\/p>\n<\/div>\n<div class=\"form-group\">\n\t<p><span class=\"wpcf7-form-control-wrap\" data-name=\"coutrylist\"><select class=\"wpcf7-form-control wpcf7-select wpcf7-validates-as-required full-width\" aria-required=\"true\" aria-invalid=\"false\" name=\"coutrylist\"><option value=\"Select Country*\">Select Country*<\/option><option value=\"Unites States\">Unites States<\/option><option value=\"Canada\">Canada<\/option><option value=\"Mexico\">Mexico<\/option><option value=\"Germany\">Germany<\/option><option value=\"Ireland\">Ireland<\/option><option value=\"India\">India<\/option><option value=\"Sweden\">Sweden<\/option><option value=\"Afghanistan\">Afghanistan<\/option><option value=\"Albania\">Albania<\/option><option value=\"Algeria\">Algeria<\/option><option value=\"Andorra\">Andorra<\/option><option value=\"Angola\">Angola<\/option><option value=\"Anguilla\">Anguilla<\/option><option value=\"Antarctica\">Antarctica<\/option><option value=\"Argentina\">Argentina<\/option><option value=\"Armenia\">Armenia<\/option><option value=\"Aruba\">Aruba<\/option><option value=\"Australia\">Australia<\/option><option value=\"Austria\">Austria<\/option><option value=\"Azerbaijan\">Azerbaijan<\/option><option value=\"Bahamas\">Bahamas<\/option><option value=\"Bahrain\">Bahrain<\/option><option value=\"Bangladesh\">Bangladesh<\/option><option value=\"Barbados\">Barbados<\/option><option value=\"Belarus\">Belarus<\/option><option value=\"Belgium\">Belgium<\/option><option value=\"Belize\">Belize<\/option><option value=\"Benin\">Benin<\/option><option value=\"Bermuda\">Bermuda<\/option><option value=\"Bhutan\">Bhutan<\/option><option value=\"Bosnia\">Bosnia<\/option><option value=\"Botswana\">Botswana<\/option><option value=\"Brazil\">Brazil<\/option><option value=\"Bulgaria\">Bulgaria<\/option><option value=\"Bolivia\">Bolivia<\/option><option value=\"Cambodia\">Cambodia<\/option><option value=\"Cameroon\">Cameroon<\/option><option value=\"Chile\">Chile<\/option><option value=\"China\">China<\/option><option value=\"Colombia\">Colombia<\/option><option value=\"Costa Rica\">Costa Rica<\/option><option value=\"Croatia\">Croatia<\/option><option value=\"Cuba\">Cuba<\/option><option value=\"Cyprus\">Cyprus<\/option><option value=\"Czech\">Czech<\/option><option value=\"Denmark\">Denmark<\/option><option value=\"Dominican\">Dominican<\/option><option value=\"Ecuador\">Ecuador<\/option><option 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value=\"Kuwait\">Kuwait<\/option><option value=\"Korea\">Korea<\/option><option value=\"Latvia\">Latvia<\/option><option value=\"Lebanon\">Lebanon<\/option><option value=\"Liberia\">Liberia<\/option><option value=\"Liechtenstein\">Liechtenstein<\/option><option value=\"Lithuania\">Lithuania<\/option><option value=\"Luxembourg\">Luxembourg<\/option><option value=\"Libya\">Libya<\/option><option value=\"Macao\">Macao<\/option><option value=\"Macedonia\">Macedonia<\/option><option value=\"Moldova\">Moldova<\/option><option value=\"Mozambique\">Mozambique<\/option><option value=\"Madagascar\">Madagascar<\/option><option value=\"Malawi\">Malawi<\/option><option value=\"Malaysia\">Malaysia<\/option><option value=\"Mali\">Mali<\/option><option value=\"Malta\">Malta<\/option><option value=\"Martinique\">Martinique<\/option><option value=\"Mauritania\">Mauritania<\/option><option value=\"Mauritius\">Mauritius<\/option><option value=\"Mayotte\">Mayotte<\/option><option value=\"Monaco\">Monaco<\/option><option value=\"Mongolia\">Mongolia<\/option><option value=\"Montenegro\">Montenegro<\/option><option value=\"Montserrat\">Montserrat<\/option><option value=\"Morocco\">Morocco<\/option><option value=\"Myanmar\">Myanmar<\/option><option value=\"Namibia\">Namibia<\/option><option value=\"Nauru\">Nauru<\/option><option value=\"Nepal\">Nepal<\/option><option value=\"Netherlands\">Netherlands<\/option><option value=\"New Caledonia\">New Caledonia<\/option><option value=\"New Zealand\">New Zealand<\/option><option value=\"Nicaragua\">Nicaragua<\/option><option value=\"Nigeria\">Nigeria<\/option><option value=\"Norfolk Island\">Norfolk Island<\/option><option value=\"Norway\">Norway<\/option><option value=\"Oman\">Oman<\/option><option value=\"Pakistan\">Pakistan<\/option><option value=\"Palau\">Palau<\/option><option value=\"Palestine\">Palestine<\/option><option value=\"Panama\">Panama<\/option><option value=\"Papua New Guinea\">Papua New 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value=\"Louisiana\">Louisiana<\/option><option value=\"Maine\">Maine<\/option><option value=\"Maryland\">Maryland<\/option><option value=\"Massachusetts\">Massachusetts<\/option><option value=\"Michigan\">Michigan<\/option><option value=\"Minnesota\">Minnesota<\/option><option value=\"Mississippi\">Mississippi<\/option><option value=\"Missouri\">Missouri<\/option><option value=\"Montana\">Montana<\/option><option value=\"Nebraska\">Nebraska<\/option><option value=\"Nevada\">Nevada<\/option><option value=\"New Hampshire\">New Hampshire<\/option><option value=\"New Jersey\">New Jersey<\/option><option value=\"New Mexico\">New Mexico<\/option><option value=\"New York\">New York<\/option><option value=\"North Carolina\">North Carolina<\/option><option value=\"North Dakota\">North Dakota<\/option><option value=\"Ohio\">Ohio<\/option><option value=\"Oklahoma\">Oklahoma<\/option><option value=\"Oregon\">Oregon<\/option><option value=\"Pennsylvania\">Pennsylvania<\/option><option value=\"Rhode Island\">Rhode Island<\/option><option value=\"South Carolina\">South Carolina<\/option><option value=\"South Dakota\">South Dakota<\/option><option value=\"Tennessee\">Tennessee<\/option><option value=\"Texas\">Texas<\/option><option value=\"Utah\">Utah<\/option><option value=\"Vermont\">Vermont<\/option><option value=\"Virginia\">Virginia<\/option><option value=\"Washington\">Washington<\/option><option value=\"West Virginia\">West Virginia<\/option><option value=\"Wisconsin\">Wisconsin<\/option><option value=\"Wyoming\">Wyoming<\/option><\/select><\/span>\n\t<\/p>\n<\/div>\n<div class=\"form-group\">\n\t<p><span class=\"wpcf7-form-control-wrap\" data-name=\"your-message\"><textarea cols=\"40\" rows=\"10\" class=\"wpcf7-form-control wpcf7-textarea full-width input-text\" aria-invalid=\"false\" placeholder=\"Your Message\" name=\"your-message\"><\/textarea><\/span>\n\t<\/p>\n<\/div>\n<div class=\"form-group\" align=\"left\">\n\n<\/div>\n<div class=\"form-group\">\n\t<p><input class=\"wpcf7-form-control wpcf7-submit has-spinner btn btn-md style1\" type=\"submit\" value=\"REQUEST SANDBOX\" \/>\n\t<\/p>\n<\/div><div class=\"wpcf7-response-output\" aria-hidden=\"true\"><\/div>\n<\/form>\n<\/div>\n\n[\/vc_column_text][vc_column_text]\n<p><span style=\"font-family: arial, helvetica, sans-serif; font-size: 12pt;\">For more info about DevAlert contact :\u00a0 <a href=\"mailto:info@emprog.com\">info@emprog.com<\/a><\/span><\/p>\n[\/vc_column_text][\/vc_column][vc_column width=&#8221;1\/4&#8243;][\/vc_column][\/vc_row]\n<\/div>","protected":false},"excerpt":{"rendered":"<p>[vc_row][vc_column width=&#8221;1\/6&#8243;][\/vc_column][vc_column width=&#8221;2\/3&#8243;][vc_empty_space height=&#8221;20&#8243;][\/vc_column][vc_column width=&#8221;1\/6&#8243;][\/vc_column][\/vc_row][vc_row][vc_column width=&#8221;1\/4&#8243;][\/vc_column][vc_column width=&#8221;1\/2&#8243;][vc_column_text] Virtual Prototyping [\/vc_column_text][vc_empty_space height=&#8221;20&#8243;][vc_column_text] We offer a leading Virtual Prototyping and Simulation platform supporting a Full System Simulation. SIM-V platform is indispensable for any embedded software development using RISC-V minimizing the complexity and &#8230;<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"template-full-width.php","meta":{"footnotes":""},"_links":{"self":[{"href":"https:\/\/www.emprog.com\/emprog\/wp-json\/wp\/v2\/pages\/2707"}],"collection":[{"href":"https:\/\/www.emprog.com\/emprog\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.emprog.com\/emprog\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.emprog.com\/emprog\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.emprog.com\/emprog\/wp-json\/wp\/v2\/comments?post=2707"}],"version-history":[{"count":18,"href":"https:\/\/www.emprog.com\/emprog\/wp-json\/wp\/v2\/pages\/2707\/revisions"}],"predecessor-version":[{"id":2743,"href":"https:\/\/www.emprog.com\/emprog\/wp-json\/wp\/v2\/pages\/2707\/revisions\/2743"}],"wp:attachment":[{"href":"https:\/\/www.emprog.com\/emprog\/wp-json\/wp\/v2\/media?parent=2707"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}