{"id":2071,"date":"2018-04-22T17:54:36","date_gmt":"2018-04-22T17:54:36","guid":{"rendered":"http:\/\/www.emprog.com\/emprog\/arm-keil-2\/"},"modified":"2018-04-22T20:33:18","modified_gmt":"2018-04-22T20:33:18","slug":"ashling","status":"publish","type":"page","link":"https:\/\/www.emprog.com\/emprog\/ashling\/","title":{"rendered":"Product Ashling"},"content":{"rendered":"
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Ashling MIPS and ARC Tools<\/h1><\/div>[\/vc_column][\/vc_row][vc_row][vc_column width=”1\/4″][\/vc_column][vc_column width=”1\/2″][vc_column_text el_class=”products-pages”]\n\n\n\n
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ARC<\/strong><\/p>\n

Opella-XD-ARC<\/strong>
\nOPELLA-XD is a high-speed cJTAG\/JTAG debug probe for embedded development on Synopsys’ DesignWare ARC configurable RISC cores. Developed in cooperation with Synopsys, the Opella-XD probe integrates with the MetaWare or GNU GDB Debuggers under Windows or Linux based hosts.<\/p>\n

\u2022 Supports all Synopsys DesignWare ARC processors including HS, EM, ARC 600 and ARC 700
\n\u2022 Target cJTAG\/JTAG clock rates up to 100MHz
\n\u2022 Target voltage range: 0.9V to 3.6V
\n\u2022 Up to 4 MB\/s high speed download
\n\u2022 Auto-conditioning for fast cJTAG\/JTAG clock frequencies
\n\u2022 Multi-core debugging support
\n\u2022 Hot-plug support for post-mortem debugging
\n\u2022 Supports Flash Programming and FPGA Programming
\n\u2022 Powered by USB interface \u2013 no external power-supply required
\n\u2022 Display\/read\/write of target system memory and peripheral registers
\n\u2022 Run\/stop control of target application including go, halt, step over, step into and step out<\/p>\n

Ultra-XD-ARC<\/strong>
\nAshling\u2019s ULTRA-XD is a high-performance real-time trace probe for embedded development and debug on Synopsys\u2019 DesignWare\u00ae ARC\u00ae EM and HS processors. Developed in cooperation with Synopsys, the Ultra-XD probe integrates with the MetaWare or GNU GDB Debuggers under Windows or Linux based hosts<\/p>\n

\u2022 RTT support for Synopsys’ DesignWare ARC EM and HS processors.
\n\u2022 Large trace storage: 4GB on-board trace storage memory in Ultra-XD Trace Probe
\n\u2022 High speed trace capture:
\n\u2022 Parallel trace (up to 16-bits)
\n\u2022 Trace port frequency up to 400MHz DDR (double-data rate)
\n\u2022 Serial Gigabit trace: up to 4 lanes at speeds of up to 6.4Gb\/s per lane
\n\u2022 50-bit, 5ns resolution timestamp generator
\n\u2022 Multi-core trace support
\n\u2022 Automatic configuration for target voltage from 0.4V to 3.6V
\n\u2022 Automatic calibration of trace clock\/data skew adjustment
\n\u2022 Supports all ARC hardware-debug standards including cJTAG, JTAG and NEXUS (Trace)
\n\u2022 38-way Mictor target connector support
\n\u2022 Ultra-XD is integrated into the MetaWare IDE providing full hardware-based debug and Real-time Trace (RTT) capabilities
\n\u2022 MetaWare IDE version MWDT J-2014.06 or later is required for Ultra-XD and RTT suppor<\/p>\n

MIPS<\/strong><\/p>\n

Opella-XD-MIPS
\nOpella-XD-MIPS is a high-speed EJTAG debug probe for embedded development on MIPS configurable RISC cores. The Opella-XD-MIPS probe integrates with Ashling’s PathFinder-XD Eclipse based source debugger under Windows or Linux based hosts<\/p>\n

\u2022 Fast, easy-to-install USB 2.0 Probe interfaces to host PC or Linux workstation
\n\u2022 Code download to target at over 3MB\/s
\n\u2022 Target EJTAG clock rates from 1KHz up to 100MHz
\n\u2022 Fast in-target Flash Programming
\n\u2022 Supports all MIPSTM hardware-debug standards: EJTAG 4.10, 3.10, 2.6x, 2.5x, 2.0x and 1.5x
\n\u2022 Wide target voltage range: 0.9V to 3.6V
\n\u2022 Versatile Target-Reset and Test-Port-Reset support
\n\u2022 Hot-plug support for post mortem debugging<\/p>\n

NXP POWER Architecture<\/strong><\/p>\n

VITRA-PPC Trace probe is a powerful networked Emulation and Trace system for embedded development with NXP ‘s Power Architecture\u00ae devices using the NEXUS 5001 on-chip debug interface.<\/p>\n

\u2022 Vitra debugging is completely non-intrusive and requires no target system resources. Together with Ashling’s PathFinder source-level debugger, Vitra provides powerful run\/stop control of embedded software, with hardware and software breakpoints.
\n\u2022 Vitra provides fast code download to the target system, and allows control and interrogation of all core-processor and system resources. Vitra incorporates high speed Ethernet, USB and serial connections to\u00a0the\u00a0host\u00a0PC.
\n\u2022 Vitra provides full Instruction Trace and Data Trace using the NEXUS 5001 standard on-chip debug interface.<\/p>\n

For more information and licensing please Contact Emprog<\/a><\/p>\n

*ARC is a trademark of Synopsys
\n*MIPS is a trademark of MIPS
\n*NEXUS 5001 is a trademark of NXP<\/p>\n<\/div>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n[\/vc_column_text][\/vc_column][vc_column width=”1\/4″][\/vc_column][\/vc_row]\n<\/div>","protected":false},"excerpt":{"rendered":"

[vc_row][vc_column][\/vc_column][\/vc_row][vc_row][vc_column width=”1\/4″][\/vc_column][vc_column width=”1\/2″][vc_column_text el_class=”products-pages”] ARC Opella-XD-ARC OPELLA-XD is a high-speed cJTAG\/JTAG debug probe for embedded development on Synopsys’ DesignWare ARC configurable RISC cores. Developed in cooperation with Synopsys, the Opella-XD probe integrates with the MetaWare or GNU GDB Debuggers under …<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"template-full-width.php","meta":{"footnotes":""},"_links":{"self":[{"href":"https:\/\/www.emprog.com\/emprog\/wp-json\/wp\/v2\/pages\/2071"}],"collection":[{"href":"https:\/\/www.emprog.com\/emprog\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.emprog.com\/emprog\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.emprog.com\/emprog\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.emprog.com\/emprog\/wp-json\/wp\/v2\/comments?post=2071"}],"version-history":[{"count":11,"href":"https:\/\/www.emprog.com\/emprog\/wp-json\/wp\/v2\/pages\/2071\/revisions"}],"predecessor-version":[{"id":2126,"href":"https:\/\/www.emprog.com\/emprog\/wp-json\/wp\/v2\/pages\/2071\/revisions\/2126"}],"wp:attachment":[{"href":"https:\/\/www.emprog.com\/emprog\/wp-json\/wp\/v2\/media?parent=2071"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}