{"id":1934,"date":"2018-04-20T23:24:17","date_gmt":"2018-04-20T23:24:17","guid":{"rendered":"http:\/\/www.emprog.com\/emprog\/tracelyzer-2\/"},"modified":"2018-04-22T20:38:43","modified_gmt":"2018-04-22T20:38:43","slug":"risc-v","status":"publish","type":"page","link":"https:\/\/www.emprog.com\/emprog\/risc-v\/","title":{"rendered":"Product RISCV"},"content":{"rendered":"
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RISC-V Solutions<\/h1><\/div>[\/vc_column][\/vc_row][vc_row][vc_column width=”1\/4″][\/vc_column][vc_column width=”1\/2″][vc_column_text]\n\n\n\n
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With its close cooperation and partnership with leading RISC-V IP and tools manufactures, Emprog is offering a one-stop-shop RISC-V complete development solution which includes the following:<\/p>\n

\u2022 RISC-V Debug Tool and IDE
\n\u2022 RISC-V SOC (System-on-chip) and IP development services
\n\u2022 RISC-V Simulation and Virtual Platforms
\n\u2022 RISC-V Embedded Services<\/p>\n

RISC-V Debug Tool and IDE<\/span><\/b><\/p>\n

\u2022 IDE\/Compiler\/Simulator\/Debugger
\n\u2022 Fully integrated Eclipse-based tools and Eclipse plug-ins
\n\u2022 RTOS awareness
\n\u2022 Provides a one-click install SDK that guarantees a positive user experience
\n\u2022 High performance JTAG debug probe
\n\u2022 High speed USB 3.0
\n\u2022 Ensures high speed download and highly efficient debugging
\n\u2022 Real Time Trace
\n\u2022 Trace capture and analysis of real-time program execution and data access
\n\u2022 Non-intrusive streaming to host PC
\n\u2022 Enables user to isolate difficult-to-find and difficult-to-reproduce software bugs
\n\u2022 Code Coverage
\n\u2022 Non-intrusive analysis and reporting
\n\u2022 Ensures all code is fully tested
\n\u2022 Performance Analysis and Profiling
\n\u2022 Identification of hot spots and bottlenecks
\n\u2022 Ensures high code efficiency<\/p>\n

RISC-V SOC (System-on-chip) and IP development services<\/span><\/b><\/p>\n

We offer RISC-V processor IP and tools for developing RISC-V cores andsubsystems while achieving the highest levels of
\nquality, performance and innovation.<\/p>\n

RISC-V IP CORES<\/span><\/b><\/p>\n

Plug-n-play RISC-V processor core delivering the key benefits of open source. Save considerable time by using a single processor architecture across all semiconductor platforms (Xilinx, Altera, ASIC, \u2026).<\/p>\n

\u2022 Differentiate with your proprietary enhancements and customizations to open source code modified by you or 3rd party RISC-V developers.
\n\u2022 Make product and business decisions independently of proprietary IP companies by owning source code to processor cores.
\n\u2022 RV32IM ISA.<\/p>\n

VERIFICATION TOOLS<\/span><\/b><\/p>\n

A powerful out-of-the-box FPGA-based RISC-V development platform created by processor experts using the most advanced hardware verification technology available.<\/p>\n

\u2022 Verify that your own or other 3rd party RISC-V cores are safe to use through rigorous independent verification.
\n\u2022 Push the envelope on differentiation knowing that any bug can be quickly detected and fixed.
\n\u2022 Use a proven infrastructure to tap the benefits of open RISC-V cores at a fraction of the cost of doing it alone.
\n\u2022 A verified RISC-V core can be up and running software in minimal time by connecting to just two standard AXI interfaces to the cores instruction and data memories.<\/p>\n

RISC-V ACCELERATION<\/span><\/b><\/p>\n

A complete product suite for integrating, verifying, and debugging embedded systems to increase software speed-power ratios 10 to 100 times.<\/p>\n

The time and effort to accelerate software shrinks up to 80% by replacing fragile ad-hoc infrastructure with correct-by-construction end-to-end links connecting software, processors, accelerators and memory.<\/p>\n

The RISC-V Acceleration tool is an essential enabler of embedded systems innovation by providing seamless interfaces and integrated debug of hardware accelerators attached to RISC-V processors. You realize these benefits whether you license the Acceleration Tool suite to develop accelerators on your own or engage us to develop them for you:<\/p>\n

\u2022 Enable highest possible levels performance\/watt by using dedicated hardware accelerators seamless accessed by function calls in embedded software.
\n\u2022 Differentiate using proprietary accelerators. Focus on your problem and leave the risky, time consuming infrastructure details to the tool suite.
\n\u2022 Save considerable time by replacing multiple processor ecosystems with one used for all domain-optimized processors (DSP, Vision, AI, \u2026).<\/p>\n

RISC-V Simulation and Virtual Platforms<\/span><\/b><\/p>\n

Virtual platform solutions enable the efficient development of embedded software through high-level modeling, high-performance simulation and advanced debugging.<\/p>\n

Technology that compresses software engineering schedules, while improving code quality, and is used at leading communications, automotive, consumer electronics and embedded processor companies worldwide.<\/p>\n

\u2022 Instruction Set Simulator
\n\u2022 Virtual Platform Development & Simulation and comes with a Model Framework Generation.
\n\u2022 Virtual Platform Simulation Acceleration
\n\u2022 CPU Model Generation
\n\u2022 MultiCore Simulation & Modelling
\n\u2022 OVP (Open Virtual Platforms) Support<\/p>\n

RISC-V Embedded Services<\/span><\/b><\/p>\n

We represent a team of 1000+ engineers with a vast range of embedded product development experience. We offer a wide range of expertise and skills in industries such as IoT, Automotive, industrial control, consumer electronics and other markets.<\/p>\n

ABOUT RISC-V<\/span><\/b><\/p>\n

RISC-V is an open, free instruction set architecture (ISA) enabling a new era of processor innovation through open standard collaboration. Under the governance of the RISC-V Foundation, RISC-V offers numerous benefits, including enabling the open source community to test and improve cores at a faster pace than closed ISAs. As the RISC-V intellectual property (IP) core is not encrypted, it can be used to ensure trust and certifications not possible with closed architectures. Portability is another benefit of the technology.<\/p>\n

Born in academia and research (UC Berkeley), RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.<\/p>\n

For more information and licensing please Contact Emprog<\/a><\/div>\n<\/div>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n[\/vc_column_text][\/vc_column][vc_column width=”1\/4″][\/vc_column][\/vc_row]\n<\/div>","protected":false},"excerpt":{"rendered":"

[vc_row][vc_column][\/vc_column][\/vc_row][vc_row][vc_column width=”1\/4″][\/vc_column][vc_column width=”1\/2″][vc_column_text] With its close cooperation and partnership with leading RISC-V IP and tools manufactures, Emprog is offering a one-stop-shop RISC-V complete development solution which includes the following: \u2022 RISC-V Debug Tool and IDE \u2022 RISC-V SOC (System-on-chip) and …<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"template-full-width.php","meta":{"footnotes":""},"_links":{"self":[{"href":"https:\/\/www.emprog.com\/emprog\/wp-json\/wp\/v2\/pages\/1934"}],"collection":[{"href":"https:\/\/www.emprog.com\/emprog\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.emprog.com\/emprog\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.emprog.com\/emprog\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.emprog.com\/emprog\/wp-json\/wp\/v2\/comments?post=1934"}],"version-history":[{"count":8,"href":"https:\/\/www.emprog.com\/emprog\/wp-json\/wp\/v2\/pages\/1934\/revisions"}],"predecessor-version":[{"id":2131,"href":"https:\/\/www.emprog.com\/emprog\/wp-json\/wp\/v2\/pages\/1934\/revisions\/2131"}],"wp:attachment":[{"href":"https:\/\/www.emprog.com\/emprog\/wp-json\/wp\/v2\/media?parent=1934"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}